1. Field of the Invention
Generally, the present disclosure relates to the fabrication of integrated circuits, and, more particularly, to transistors having strained channel regions by using embedded Si/Ge (silicon/germanium) to enhance charge carrier mobility in the channel regions of the transistors.
2. Description of the Related Art
The fabrication of complex integrated circuits requires the provision of a large number of transistor elements, which represent the dominant circuit element for complex circuits. For example, several hundred millions of transistors may be provided in presently available complex integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. In CMOS circuits, complementary transistors, i.e., P-channel transistors and N-channel transistors, are used for forming circuit elements, such as inverters and other logic gates, to design highly complex circuit assemblies, such as CPUs, storage chips and the like. During the fabrication of complex integrated circuits using CMOS technology, transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, or generally a field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. For example, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions to provide low sheet and contact resistivity in combination with a desired channel controllability. Moreover, the gate dielectric material may also be adapted to the reduced channel length in order to maintain the required channel controllability. However, some mechanisms for maintaining a high channel controllability may also have a negative influence on the charge carrier mobility in the channel region of the transistor, thereby partially offsetting the advantages gained by the reduction of the channel length.
Since the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques and may also contribute to less pronounced performance gain due to mobility degradation, it has been proposed to enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby enabling a performance improvement that is comparable with the advance to a technology standard requiring extremely scaled critical dimensions, while avoiding or at least postponing many of the process adaptations associated with device scaling.
One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region for a standard crystallographic configuration of the active silicon material, i.e., a (100) surface orientation with the channel length aligned to the <110> direction, increases the mobility of electrons, which in turn may directly translate into a corresponding increase in conductivity. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach, since strained silicon may be considered as a “new” type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.
Consequently, it has been proposed to introduce, for instance, a silicon/germanium (Si/Ge) material next to the channel region to induce a compressive stress that may result in a corresponding strain. When forming the Si/Ge material, the drain and source regions of the PMOS transistors are selectively recessed to form cavities, while the NMOS transistors are masked, and subsequently the silicon/germanium material is selectively formed in the cavities of the PMOS transistor by epitaxial growth.
Although the technique has significant advantages in view of performance gain of P-channel transistors and thus of the entire CMOS device, it turns out, however, that, in advanced semiconductor devices including a large number of transistor elements, an increased variability of device performance may be observed, which may be associated with the above-described technique for incorporating a strained silicon/germanium alloy in the drain and source regions of P-channel transistors, in particular when the offset of the silicon/germanium material from the channel region is to be reduced in view of increasing the finally achieved strain, as will be described in more detail with reference to FIGS. 1a-1e. 
FIG. 1a schematically illustrates a cross-sectional view of a conventional semiconductor device 100 comprising a P-channel transistor 150A and an N-channel transistor 150B, wherein the performance of the transistor 150A is to be enhanced on the basis of a strained silicon/germanium alloy, as explained above. The semiconductor device 100 comprises a substrate 101, such as a silicon substrate, which may have formed thereon a buried insulating layer 102. Furthermore, a crystalline silicon layer 103 is formed on the buried insulating layer 102, thereby forming a silicon-on-insulator (SOI) configuration. An SOI configuration may be advantageous in view of overall transistor performance since, for instance, the parasitic junction capacitance of the transistors 150A, 150B may be reduced compared to a bulk configuration, i.e., a configuration in which a thickness of the silicon layer 103 may be significantly greater than a vertical extension of the transistors 150A, 150B into the layer 103. The transistors 150A, 150B may be formed in and above respective “active” regions, generally indicated as 103A, 103B, respectively, wherein the active regions may be separated by an isolation structure 104, such as a shallow trench isolation. In the manufacturing stage shown, the transistors 150A, 150B comprise a gate electrode structure 151, which may be understood as a structure including a conductive electrode material 151A, representing the actual gate electrode, which may be formed on a gate insulation layer 151B, thereby electrically insulating the gate electrode material 151A from a channel region 152 located within the corresponding active regions 103A, 103B, respectively. Furthermore, the gate electrode structures 151 may comprise a cap layer 151L, for instance comprised of silicon nitride. Furthermore, a spacer structure 105 may be formed on sidewalls of the gate electrode structure 151 in the transistor 150A, thereby encapsulating, in combination with the cap layer 151L, the gate electrode material 151A. On the other hand, a mask layer 105A may be formed above the transistor 150B, thereby encapsulating the corresponding gate electrode material 151A and also covering the active region 103B. Moreover, a mask 106, such as a resist mask and the like, may be formed to cover the mask layer 105A while exposing the transistor 150A.
The conventional semiconductor device 100 as shown in FIG. 1a may be formed on the basis of the following process strategy. The active regions 103A, 103B may be defined on the basis of the isolation structure 104, which may be formed by using well-established photolithography, etch, deposition and planarization techniques. Thereafter, the basic doping level in the corresponding active regions 103A, 103B may be established, for instance, by implantation processes performed on the basis of an appropriate masking regime. Next, the gate electrode structures 151 are formed by using complex lithography and patterning regimes to obtain the gate electrode material 151A and the gate insulation layer 151B, wherein the cap layer 151L may also be patterned. Next, the mask layer 105A may be deposited, for instance, by well-established low pressure chemical vapor deposition (CVD) techniques, thereby forming silicon nitride, possibly in combination with a silicon dioxide material as an etch stop liner. The low pressure CVD techniques may, although providing a high degree of controllability, nevertheless exhibit a certain non-uniformity across the substrate 101, which may result in an increased thickness at the substrate edge compared to the center of the substrate. Consequently, upon forming the mask 106 and exposing the device 100 to an anisotropic etch ambient for forming the spacer structure 105 from the previously deposited mask layer 105A, a certain degree of non-uniformity of the resulting width 105W may be created, which may, for instance, result in slightly increased width at the periphery of the substrate 101 compared to central areas of the substrate 101. Since the spacer structure 105 may substantially define a lateral offset of a cavity to be formed in the active region 103A by anisotropic etch techniques, the corresponding lateral offset may also vary slightly according to the non-uniformities introduced during the deposition of the mask layer 105A and the performing of the subsequent anisotropic etch process. On the other hand, in sophisticated applications, a lateral offset of a corresponding strained silicon/germanium alloy may be reduced in view of enhancing the overall strain in the adjacent channel region 152, thereby requiring the width 105W to be reduced to position the strained silicon/germanium alloy closer to the channel region 152. Typically, the strain in the channel region 152 may increase over proportionally for a reduced width 105W so that, in process strategies to provide a moderately small width 105W, the variability caused by the deposition of the layer 105A and the subsequent etch process may be increased over proportionally, thereby contributing to a high degree of variability of the resulting performance of the transistors 150A.
FIG. 1b schematically illustrates the semiconductor device 100 during an anisotropic plasma assisted etch process 107, in which appropriate etch chemistries, for instance on the basis of hydrogen bromide and the like, may be used in combination with appropriate organic additives so that the corresponding anisotropic etch behavior may be obtained in combination with appropriately selected plasma conditions. However, as explained above, a certain degree of variability may also be induced during the plasma assisted etch process 107, thereby also contributing to the overall variability, in particular if highly sophisticated transistors are considered in which even a minute difference in the lateral offset may thus result in a significant change of transistor performance. Consequently, due to the varying width 105W caused by the preceding deposition of the layer 105A and the corresponding anisotropic etch process for forming the spacer structure 105, possibly in combination with the anisotropic etch process 107 used for forming respective cavities 107A, the position and size thereof may also exhibit a corresponding degree of variability.
FIG. 1c schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. That is, after forming the cavities 107A, the mask 106 (FIG. 1b) is removed and a selective epitaxial growth process is performed to deposit a silicon/germanium alloy 109 in the transistor 150A, while the transistor 150B is covered by the mask layer 105A. Corresponding selective epitaxial growth recipes are well established, in which the corresponding process parameters, such as pressure, temperature, precursor flow rates and the like, are appropriately selected to obtain a significant deposition of the silicon/germanium material on exposed crystalline silicon surfaces, while a corresponding material deposition on dielectric surface areas is significantly reduced or even negligible. Thus, the silicon/germanium material 109 may be grown in a strained state, since the natural lattice constant of silicon/germanium is greater than the lattice constant of silicon, thereby obtaining a compressively strained material, which may also result in a corresponding compressive strain in the adjacent channel region 152. The magnitude of the compressive strain may depend on the position and the size of the previously formed cavities and on the germanium concentration within the material 109. Thus, for given process parameters during the selective epitaxial growth process for forming the material 109, the variability of the preceding manufacturing processes for forming the mask layer 105A, patterning the spacer structure 105 and forming the cavities 107A may thus result in a certain non-uniformity of transistor performance across the substrate 101.
FIG. 1d schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage in which the mask layer 105A, the spacer structure 105 and the cap layers 151L (see FIG. 1c) are removed, which may be accomplished by well-established selective etch techniques. Thereafter, the further processing may be continued by forming drain and source regions according to the device requirements.
FIG. 1e schematically illustrates the semiconductor device 100 in a manufacturing stage in which the basic transistor configuration is substantially completed. As illustrated, the transistors 150A, 150B may comprise a sidewall spacer structure 153, which may include one or more spacer elements 153A, possibly in combination with corresponding etch stop liners 153B, depending on the required complexity of the dopant profile of drain and source regions 154. The spacer structure 153 may be formed in accordance with well-established techniques, i.e., by depositing the etch stop liner 153B and a corresponding mask layer which may then be patterned by anisotropic etch processes to form the spacer element 153A. Prior to forming the spacer structure 153, appropriate implantation processes may be performed to define extension regions 154E, which in combination with deep drain and source areas 154D, which may be formed on the basis of the spacer structure 153, represent the drain and source regions 154. Thereafter, the dopants may be activated by annealing the device 100, thereby also re-crystallizing, at least to a certain degree, implantation-induced damage. Thereafter, the further processing may be continued by forming metal silicide regions and forming a corresponding contact structure, possibly on the basis of stressed dielectric materials, in accordance with well-established process strategies. As explained above, for sophisticated applications, performance of the transistor 150A may be substantially determined by the strain-inducing mechanism provided by the silicon/germanium alloy 109, wherein the moderately high degree of variability, in particular for a desired reduced lateral offset of the silicon/germanium material 109 from the channel region 152, may cause a reduced production yield, while in other cases the potential of the strain-inducing mechanism provided by the material 109 may not be fully exploited since a corresponding offset from the channel region 152 has to be maintained greater than desirable.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.